The ion implantation step is followed by an annealing step which normally involves a high temperature of 700xc2x0 C. or higher to activate the implanted impurity atoms in the shallow source/drain regions 16 and to cure the damage caused by the physical impact to the crystal structure of the silicon substrate 10 when the impurity atoms are implanted thereto. Sidewall spacers 18 are then formed on the side surfaces of the gate dielectric 12 and gate electrode 14, as depicted in FIG. 3.
Subsequently, source/drain regions 20 are formed by ion implanting impurity atoms, e.g., boron or phosphorus, at the impurity implantation concentration and energy higher than those from the first annealing process, by utilizing the gate electrode 14 and the sidewall spacers 18 as a mask, as depicted in FIG. 4. Once again, the annealing process is performed at a high temperature of 700xc2x0 C. or higher to activate the implanted impurity atoms in the source/drain regions 20 and to cure the damage caused by the implantation impact.
As transistor dimensions approached one micron in diameter, conventional parameters resulted in intolerably increased resistance between the active region 20 and conductive interconnect lines formed subsequently to interconnect various device elements in the integrated circuit device. The principle way of reducing such contact resistance is by forming a metal silicide atop the source/drain regions 20 and the gate electrodes 14 prior to application of the conductive film for formation of the various conductive interconnect lines. The most common metal silicide materials are CoSi2 and TiSi2.
As depicted in FIG. 5, a metal layer 22 is typically provided by first applying a thin layer of, for example, titanium, atop the wafer which contacts the source/drain regions 20. Then, the wafer is subjected to one or more annealing steps at the temperature of 800xc2x0 C. or higher. This causes the titanium layer 22 to selectively react with the silicon of the source/drain regions 20 and the gate electrodes 14, thereby forming a metal silicide (TiSi2) layer 24 selectively on the source/drain regions 20 and the gate electrodes 14. Such a process is referred to as a salicide (self-aligned silicide) process because the TiSi2 layer 24 is formed only where the titanium material directly contacts the silicon source/drain regions 20 and the polycrystalline silicon gate electrode 14. Following the formation of the silicide layer 24, as depicted in FIG. 7, an interlayer dielectric film 26 is deposited over the entire surface of the substrate 10, and an interconnect process is performed (not shown) to provide conductive paths by forming via holes through the interlayer dielectric 26 and filling the via holes with a conductive material, e.g., tungsten.
As the dimensions of the MOS transistor are further scaled down to submicron and nanometer dimensions, the thickness of the gate oxide is also scaled down accordingly. However, such excessively reduced thickness of the gate oxide causes charge carrier leakage by tunneling effect, thereby leading to faster degradation of the MOS transistor.
To solve this problem, a high k (dielectric constant) gate dielectric, e.g., ZrO2, HfO2, InO2, LaO2, TaO2, was introduced to replace the silicon oxide for submicron MOS devices. However, it has been also observed that the high k gate dielectric becomes thermally unstable during the high temperature process steps for fabrication of the MOS transistor. For example, as mentioned above, the source/drain region activation annealing steps in FIGS. 2 and 4 and the silicidation step in FIG. 6 are normally performed at a temperature of at least 700xc2x0 C. or higher, or in some cases at a temperature of 1000xc2x0 C. or higher. At such a high temperature, tantalum oxide (Ta2O5), another high k gate dielectric, is transformed from amorphous to crystalline, which causes charge carrier leakage. In addition, at such a high temperature, tantalum oxide undesirably interacts with the underlying silicon substrate or overlying polysilicon gate electrode of the MOS transistor.
To solve this problem, a metal gate electrode has been introduced to avoid the reaction between the high k gate dielectric and the polysilicon gate electrode during the high temperature processing steps. For example, as described in the U.S. Pat. No. 5,960,270 by Misra, et al. a metal deposition process was proposed to form a metal gate layer by depositing molybdenum, tungsten, tungsten silicide, nickel silicide, or titanium nitride. However, it has been also observed that the metal atoms from the gate electrode diffuse into the gate dielectric, thereby causing faster degradation of the high k gate dielectric, and both the high k gate dielectric and the metal gate electrode suffer structural stress from such high temperature process steps. Also, since the metal or metal silicide layer is deposited entirely over the semiconductor structure, it has been observed that it is difficult to controllably remove the unnecessary portions of the deposited metal or metal silicide layer to shape a metal or metal silicide gate due to the material unity.
Thus, there is a continuing need for improved methods that enable implementation of a reliable gate structure in submicron MOS transistors without the undesirable side effects and complicated process steps.
These and other needs are met by the present invention that provides a method for forming a self-aligned metal silicide gate on a gate dielectric formed of oxynitride or a nitride/oxide stack within semiconductor structures. The method includes forming a precursor having a substrate with active regions separated by a channel, and a temporary gate over the channel and between dielectric structures. The temporary gate is removed to form a recess with a bottom and sidewalls between the dielectric structures. A gate dielectric formed of oxynitride or a nitride/oxide stack is formed in the recess on the bottom and sidewalls. Amorphous silicon is deposited over the semiconductor structure and the amorphous silicon is removed except for a portion in the recess. A metal is formed over the semiconductor structure, and annealing is performed to cause the metal and the portion of the amorphous silicon in the recess to react to form a self-aligned metal silicide gate. Finally, the metal remaining unreacted after the annealing is removed from the semiconductor structure.
Hence, in accordance with an aspect of the present invention, the amorphous silicon deposited over the semiconductor structure is removed except for a portion in the recess, which enables the portion in the recess to selectively interact with the overlying metal, thereby forming the self-aligned metal silicide gate selectively within the recess. Since the silicidation between the silicon and the metal occurs selectively in the recess, and other portions of the metal remain unchanged, the remaining portions of the metal can be easily removed, by manipulating the etching selectivity between the metal silicide and the metal. Also, since the dielectric is formed of oxynitride or a nitride/oxide stack, which is less likely to become unstable during a high temperature silicidation process, the silicidation process needs not to performed below a certain temperature, e.g., 600xc2x0 C. to ensure the reliability of conventional silicon oxide or high k gate dielectrics, and therefore a wider range of metal materials can be selected to form the metal silicide gate.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.